1. Field of the Invention
The present invention relates to a chip stacked structure, and more particularly, to a stack chip stacked structure.
2. Description of Related Art
With process technologies of integrated circuit (IC) develop rapidly, the integration density of a chip inner circuit increases and an area for the conductive lines decreases. With the reduction of the area of pads and metal wires, continuous improvements of the chip stacked technology are required to adapt for more miniaturized chip.
The popularity of the high-end cell phones drives the demand of high-capacity memory wherein the high-capacity memory applied to the high-end cell phones requires high-capacity and small volume, so that traditional chip structure can not satisfy the requirements thereof completely. The 3D stacked structure technology stacks chips and then connects the stacked chips, which increases over two times density on same chip and becomes the main technique for solving high-density memory presently. However, the stacked chip structure has to connect the stacked chips, a more complex process and lower yield, and is disadvantageous to mass-production.